Field
Aspects of the present disclosure relate generally to memories, and in particular, to a system and method for reducing gate-oxide voltage stress during programming of memory cell devices.
Background
Often, an integrated circuit (IC), such as a System on Chip (SOC), includes a one-time-programmable (OTP) memory that allows one or more cores of the IC to permanently write data to the memory. The OTP memory typically does not contain data when the IC is manufactured. During initialization or subsequently throughout the course of operation of the IC, one or more cores may permanently write data to the OTP, such as, for example, calibration data, initialization data, identification data, or other data as needed.
An OTP memory typically includes a two-dimensional array of memory cells. Memory cells common to rows are coupled to corresponding word lines (WLs) of the memory. Memory cells common to a column are coupled to corresponding bit lines (BLs) of the memory. Each memory cell of an OTP memory may be configured as an electronic fuse (EFUSE) type cell, where the cell includes a fuse element coupled in series with a transistor (e.g., in series with the drain and source of a field effect transistor (FET)) between the corresponding bit line (BL) and a power rail VSS (e.g., ground). Each transistor of each memory cell includes a control terminal (e.g., gate) coupled to the corresponding word line (WL).
Generally, the programming of (writing data to) an OTP memory may be performed a single-bit at a time. In this regard, the voltages on the word line (WL) and the bit line (BL) corresponding to the memory cell (to-be-programmed) are both raised to programming voltage (e.g., 1.8V). This produces a current through the corresponding fuse element and FET sufficient to blow the fuse element (e.g., produce an open in the fuse metallization due to electromigration). A memory cell that has its fuse blown may be assigned a bit value (e.g., a logic one (1)), and a memory cell that has not had its fuse blown may be assigned another bit value (e.g., a logic zero (0)).
Generally, the programming voltage of an OTP memory cell is higher than a rating for core devices (e.g., FETs). For example, a core FET may have a voltage rating of no more than 1.0V, whereas a programming voltage of 1.8V would exceed the rating of such core device. As a consequence, OTP memory cells have been traditionally configured with higher rated device, such as those used for input/output (I/O) operations where the gate oxide of such devices are made thicker to be able to withstand the programming voltage. However, using higher-rated devices has a drawback as the OTP memory has to occupy a substantial amount of area of an IC.
It would be desirable to implement an OTP memory using lower rated devices, such as core devices, to reduce the IC area required to implement the memory, and at the same time, reduce stress to the core devices associated with the programming voltage.